Useful links: Verilog

Books & Guides Language Tools & Utilities Models

Books & Guides

	Books (Search for Verilog)
	All IEEE standards can be obtained from http://www.ieee.org
	On-line Verilog quick reference guide
	Alternate Verilog FAQ
	Hot PLI Stuff
	Usenet groups: comp.lang.verilog, comp.lang.synthesis
	Celia's Verilog & EDA Web page
	Quick Reference Cards: Comit, Qualis
	Free stuff
	Understanding CRCs
	Synthesis and scripting techniques for designing multi-asynchronous clock designs
	Peter Chambers "10 commandments of excellent design"
	Public domain verilog resources
	PLI info
	Verilog HDL Coding Style Guide
	The HDL Page (EDAI)
	"Moving Data Across Asynchronous Clock Boundaries" by Peter Alfke
	Verilog.com
	Alternate Verilog FAQ
	Rajesh Bawankule's Verilog Center
	CSCI 320 Computer Architecture Verilog Manual
	Verilog.Net - Premiere List of Verilog Resources on the Internet
	Celia's Verilog & EDA Web Page
	VERILOG INTRODUCTION FOR DIGITAL DESIGN
	Verilog HDL
	Home of Verilog Quickstart
	Open Directory - Computers: Programming: Languages: Verilog
	FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
	Verilog-mode : SureFire
	Verilog(TM) HDL LRM project : M. Smith
	Bucknell Verilog Manual
	A Brief Introduction to PLI (Programming Language Interface)
	Jimen Ching's Web Page
	AMIS \| Verilog
	EE271/272 Verilog FAQ : Stanford
	Silicon Sorcery
	Tek-Tips Forums for computer professionals
	verilog - best of the web - hdl
	HDL, VHDL, Verilog and FPGA Training from Esperan
	FPGA, VHDL, Verilog Newsgroups
	Comit Systems - Free Downloads
	Riviera Verilog PLI Interface
	ECE347 Verilog Resources : CMU
	verilog - internet resources (verilog)
	ASIC laboratory Heidelberg
	Verilog Computer-Based Training Course CD-ROM
	Verilog : UA
	VERILOG SOURCES
	Qualis Course: Jump Start for Verilog Verification
	Verilog Links
	Verilog Information : UI
	Using Verilog
	Mixed-Signal Modeling with Vanilla VHDL and Verilog
	Verilog
	VERILOG HDL RESOURCES
	Multisim Education Verilog
	Comprehensive Verilog Design � 4 days : TM Associates
	EWB Multisim VHDL/Verilog Design/Simulation
	Verilog : NEU
	EKV v2.6 Verilog-A implementation
	Verilog Exercises
	Verilog Models
	Verilog Tutorial Frame 6
	Intro to Verilog v5 : Xilinx
	comp.lang.verilog Newsgroup FAQs
	ASPN : Modules
	EWB Multisim Verilog
	Verilog-A Release in SmartSpice
	Verilog Resources
	Rajesh Bawankule's Verilog Center: Free Stuff
	VERILOG SOURCES
	CSCI Computer Architecture Verilog Manual
	Programmer's Oasis - Verilog
	HDL Planet's Verilog Page
	ECE 475 Verilog Manual : CU
	Abstract State Machines: VHDL and Verilog

Language

	Verilog HDL Working Group : Group in charge of Verilog HDL, IEEE Std 1364
	Verilog Synthesis Interoperability Working Group: Group in charge of development of RTL standard IEEE Std 1364.1
	Verilog 2000: What's new
	Verilog tutorial
	Verilog-93 syntax
	Online Verilog tutorial
	Tutorial on Verilog
	Verilog Quick Reference Card
	Verilog Tutorials (OptiMagic)
	Introduction to Verilog
	Verilog HDL On-line Quick Reference, by Sutherland HDL, Inc., ...
	Verilog-AMS Home
	Verilog-2001 Information Page by Sutherland HDL, Inc.
	VHDL and Verilog References and Tutorials : Optimagic
	Verilog tutorials for beginners : 1001 Tutorials
	Designer's Guide to Verilog : Doulos
	Learn Verilog On-line
	Verilog tutorials online!
	VERILOG TUTORIAL
	An Introduction to Verilog
	Verilog HDL On-line Quick Reference body
	CSCI 320 Computer Architecture Handbook on Verilog HDL
	Verilog HDL Coding Style Guide
	Verilog Style Manual
	Verilog Quick Ref Card
	Verilog-XL Reference -- Table Of Contents
	Verilog HDL QUICK REFERENCE CARD

Tools & Utilities

	Verilog for emacs and Xemacs
	hdlmaker: Generating top-level netlist from lower-level blocks
	mktree: Creating module connection files
	Free Verilog simulator: Icarus Verilog
	Verilator: Free Verilog to C++ simulator
	C-like file I/O
	Verilog HDL Obfuscator
	Free Verilog Simulator, Windows 98: SILOS III
	Source Navigator
	Perl/Python/Tcl Interface to VPI
	Free Viewer
	Parsers
	Instance name extraction
	Free timing diagram editor
	Free Verilog PC simulator: cygwin
	Connect modules (Topweaver)
	Interactive Design and Simulation System (IDaSS)
	SFL to Verilog
	Icarus Verilog
	Mac's Emacs Mode
	v2html - verilog to html converter
	Verilog HDL Simulators - EDA Tools for FPGA and ASIC Digital ...
	Source Navigator for Verilog
	Freeware EDA Tools Page
	Aldec - Free Downloads
	Ver Structural Verilog Compiler
	Free Verilog HDL Simulator - Silos Free Demo Software
	Verilog-Perl : Wilson Synder
	Verilog Formal Equivalence Project
	Verilog++: a Verilog preprocessor
	v2html - Rough Verilog Parser
	Verilog Tag2 Script
	Verilog PreProcessors
	VTM - Verilog Template Maker
	ScriptSim Verilog PLI Perl/Python/Tk Interface Introduction
	verilog2vhdl (tm) Verilog to VHDL translation
	Verilog Model Generators: VeriGen and VeriTest
	File I/O for Verilog models
	Netman: Verilog Netlist manager/viewer
	Inst Verilog Generation Functions
	Perlilog: IP integration Tool

Models

	Synthesizable microprocessor
	RTL descriptions of Flip-flops
	16bit risc cpu core
	Utopia 4
	UART design, also here, and here
	Ethernet (802.3) MAC model
	Flash Memory
	I2C Slave Interface
	8x8 DCT, fully pipelines
	QNR, Quantization & Rounding unit
	Run-Length encoder
	Huffman Encoder
	Huffman Decoder
	Hardware Dividers
	Triple DES
	USB 1.1 Phy
	Asynchronous Serial IO Controller
	Single Slot PCM Controller
	USB 1.1 Function IP Core
	Generic FIFOs
	CPU/Microcontroller (PIC Clone) IP Core
	DES IP Core
	Single Precision FPU (IEEE-754 compliant) IP Core
	USB 2.0 Function (Slave) IP Core
	DMA/Bridge IP Core
	Advanced Memory Controller IP Core
	AC97 Controller IP Core
	WISHBONE Interconnect Matrix
	SSRAM Interface
	ATA/ATAPI Host Controller
	I2C Master Controller
	VGA/LCD Controller
	CORDIC Core
	Video Compression System
	Open 54x DSP clone
	PCI Model
	Verilog HDL Examples : Altera
	CMOSexod.com your source of free Verilog/VHDL IPs.
	VERILOG description : UCB
	VHDL/Verilog Models : Denali
	Verilog,HDL,bus interface,core logic,bus architecture,IP blocks, ...
	Free RISC8 (Verilog)
	The RISC8 Verilog core
	DCD - Digital Core Design - VHDL and Verilog IP Cores supplier

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Last updated: August 11, 2003